W79L632A register define

Posted by: 邱小新 at 上午9:56 in
#include <8052.h> /* ------------------------------------------------ */ /* The SFRs reside in the register locations 80-FFh */ /* and are accessed by direct addressing only. */ /* ------------------------------------------------ */ __sfr __at (0x8E) CKCON; __sfr __at (0x92) P4CONA; __sfr __at (0x93) P4CONB; __sfr __at (0x9F) CHPCON; __sfr __at (0xA5) P4; __sfr __at (0xA9) SADDR; __sfr __at (0xAB) ROMCON; __sfr __at (0xAC) SFRAL; __sfr __at (0xAD) SFRAH; __sfr __at (0xAE) SFRFD; __sfr __at (0xAF) SFRCN; __sfr __at (0xC3) PWM5; __sfr __at (0xC4) PMR; __sfr __at (0xC7) TA; __sfr __at (0xCE) PWMCON2; __sfr __at (0xCF) PWM4; __sfr __at (0xD8) WDCON; __sfr __at (0xD9) PWMP; __sfr __at (0xDA) PWM0; __sfr __at (0xDB) PWM1; __sfr __at (0xDC) PWMCON1; __sfr __at (0xDD) PWM2; __sfr __at (0xDE) PWM3; __sfr __at (0xE8) EIE; __sfr __at (0xF8) EIP; /* ------------------------------------------------ */ /* The SFRs that are bit addressable are those */ /* whose addresses end in 0 or 8. */ /* ------------------------------------------------ */ __sbit __at (0xD8) RWT ; /* protected bit */ /* Mnemonic:WDCON, bit 0 */ __sbit __at (0xD9) EWT ; /* protected bit */ __sbit __at (0xDA) WTRF; __sbit __at (0xDB) WDIF; /* protected bit */ __sbit __at (0xDC) WD_4; /* not used */ __sbit __at (0xDD) WD_5; /* not used */ __sbit __at (0xDE) POR ; /* protected bit */ /* Mnemonic:WDCON, bit 6 */ __sbit __at (0xDF) WD_7; /* not used */ //---------------------------------------------------------------------- // EIE register 0xE8 (Extended Interrupt Enable register) // 7 6 5 4 3 2 1 0 // X X X EWDI X X X X //---------------------------------------------------------------------- __sbit __at (0xEC) EWDI; //---------------------------------------------------------------------- // EIP register 0xF8 (Extended Interrupt Priority register) // 7 6 5 4 3 2 1 0 // X X X PWDI X X X X //---------------------------------------------------------------------- __sbit __at (0xFC) PWDI;//---------------------------------------------------------------------- // PWMCON1 register 0xDC (PWM control 1 register) // 7 6 5 4 3 2 1 0 // PWM3OE PWM2OE ENPWM3 ENPWM2 PWM1OE PWM0OE ENPWM1 ENPWM0 //---------------------------------------------------------------------- #define PWM3OE 0x80 // Output enable for PWM3 #define PWM2OE 0x40 // Output enable for PWM2 #define ENPWM3 0x20 // Enable PWM3 #define ENPWM2 0x10 // Enable PWM2 #define PWM1OE 0x08 // Output enable for PWM1 #define PWM0OE 0x04 // Output enable for PWM0 #define ENPWM1 0x02 // Enable PWM1 #define ENPWM0 0x01 // Enable PWM0 //---------------------------------------------------------------------- // PWMCON2 register 0xCE (PWM control 2 register) // 7 6 5 4 3 2 1 0 // X X X X PWM5OE PWM4OE ENPWM5 ENPWM4 //---------------------------------------------------------------------- #define PWM5OE 0x08 // Output enable for PWM5 #define PWM4OE 0x04 // Output enable for PWM4 #define ENPWM5 0x02 // Enable PWM5 #define ENPWM4 0x01 // Enable PWM4 //---------------------------------------------------------------------- // PCON register 0x87 (power control register) // 7 6 5 4 3 2 1 0 // SMOD X X X GF1 GF0 PD IDL //---------------------------------------------------------------------- #define PCON_SMOD 0x80 // double baud rate, when serial mode 1,2,3 #define PCON_GF1 0x08 // general purpose #define PCON_GF0 0x04 // general purpose #define PCON_PD 0x02 // entry power down mode #define PCON_IDLE 0x01 // entry idle mode //---------------------------------------------------------------------- // CHPCON register 0x9F (ISP control register) protected byte // 7 6 5 4 3 2 1 0 // SWRST X LDAP X X X LSEL ENP //---------------------------------------------------------------------- #define CHP_SWRST 0x80 // Set this bit to launch a whole device reset // that is same as asserting high th RST pin. #define CHP_LDAP 0x20 // read only. High: the device is excuting the program in LDFlash // Low: the device is excuting the program in APFlashs #define CHP_LSEL 0x02 // Set to high to route the device fetching code from LDFlash #define CHP_ENP 0x01 // Set this be to launch the ISP mode

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